This relates generally to analog-to-digital converters, and more specifically, to massively parallel analog-to-digital converters. Massively parallel analog-to-digital converters may be included within image sensors.
Modern electronic devices such as cellular telephones, cameras, and computers often use digital image sensors. Image sensors (sometimes referred to as imagers) may be formed from a two-dimensional array of image sensing pixels. The array of image sensing pixels are typically arranged in pixel rows and columns. Each pixel includes a photosensitive layer that receives incident photons (light) and converts the photons into electrical charge. Column sensing circuitry is typically coupled to each pixel column for reading out image signals from the image pixels.
Conventional image sensors often include analog-to-digital conversion circuitry for converting analog signals generated from the image pixels to digital signals. In one configuration, an image sensor is provided with charge sharing successive approximation register (SAR) analog-to-digital converters (ADCs). A “charge sharing” SAR ADC has a feedback digital-to-analog converter (DAC) that is configured to successively add pre-charged capacitors in parallel based on the output of a comparator. This is different from the more traditional “charge redistribution” SAR ADC where all capacitance of the feedback DAC is initially connected at the beginning of the conversion and individual capacitors are switched to different reference voltage levels based on the output of the comparator.
As described above, the capacitance of the feedback DAC in a charge sharing ADC changes every cycle. Successively adding in capacitors will change the corresponding input charge. Due to non-idealities, the comparator will exhibit some non-zero comparator offset, which will affect the equivalent input voltage in every cycle of the operation. In other words, the charge sharing SAR ADC is very sensitive to comparator offset, which can limit the use of the charge sharing SAR architecture to less than 10 bits.
It is within this context that the embodiments herein arise.